Dr. Florian Zaruba

Processor and accelerator design.

About

My name is Florian and I am currently at Axelera AI. I did my PhD at the Integrated Systems Laboratory of ETH Zurich. My research interests include the design of very large scale integration circuits, with a particular focus on application-specific integrated circuits and their use in high-performance computing. Please don't hesitate to get in touch.

Selected publications

  1. Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point ComputingFlorian Zaruba, Fabian Schuiki and Luca BeniniHotChips 2020
  2. FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision ComputingStefan Mach, Fabian Schuiki, Florian Zaruba and Luca BeniniIEEE Transactions on Very Large Scale Integration (VLSI) Systems
  3. Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive WorkloadsFlorian Zaruba, Fabian Schuiki, Torsten Hoefler and Luca BeniniIEEE Transactions on Computers
  4. Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue CoresFabian Schuiki, Florian Zaruba, Torsten Hoefler and Luca BeniniIEEE Transactions on Computers
  5. The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and PerformanceFlorian Zaruba, Fabian Schuiki, Stefan Mach and Luca Benini26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019
  6. Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOIMatheus Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner and Luca BeniniIEEE Transactions on Very Large Scale Integration (VLSI) Systems
  7. The Cost of Application-class Processing: Energy and Performance Analysis of a Linux-ready 1.7-GHz 64-bit RISC-V Core in 22-nm FDSOI TechnologyFlorian Zaruba and Luca BeniniIEEE Transactions on Very Large Scale Integration (VLSI) Systems 27.11 (2019): 2629–2640
  8. OpenPiton + Ariane: The First Open-Source, SMP Linux-booting RISC-V System Scaling From One to Many CoresJonathan Balkind, Katie Lim, Fei Gao, Jinzheng Tu, David Wentzlaff, Michael Schaffner, Florian Zaruba and Luca BeniniThird Workshop on Computer Architecture Research with RISC-V (CARRV)
  9. BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA ResearchJonathan Balkind, Katie Lim, Michael Schaffner, Fei Gao, Grigory Chirkov, Ang Li, Alexey Lavrov, Tri M. Nguyen, Yaosheng Fu, Florian Zaruba, Kunal Gulati, Luca Benini and David WentzlaffASPLOS 2020

Full list on Google Scholar.

Talks

  1. Ariane: An Open Source 64-bit RISC-V Application Class Processor and Latest ImprovementsRISC-V Workshop
  2. Updates on PULPinoRISC-V Workshop

Chips

  1. Baikonur GF22FDX · 2019Successor of Kosmodrom with two Ariane cores and 25 Snitch cores.
  2. Billywig UMC L65 · 2019First ASIC implementation of a Snitch cluster.
  3. Kosmodrom GF22FDX · 2018Two Ariane cores and a neural network accelerator (NTX).
  4. Poseidon GF22FDX · 2018One Ariane core coupled to a PULP-based SoC.
  5. Scarabaeus UMC L65 · 2018Student design, partially under my supervision: one Ariane core and a tensor DMA.
  6. Atomario UMC L65 · 2018Multi-cluster PULP implementation with an atomic adapter.
  7. Drift UMC L65 · 2018Different integer divider implementations.
  8. Imperio UMC L65 · 2015My first chip as a Master's student: a PULPino system.